MachXO2 Speed Grade -4 Cell Timings

DP8KC:REGMODE_A=NOREG,REGMODE_B=NOREG
DP8KC:REGMODE_A=NOREG,REGMODE_B=OUTREG
DP8KC:REGMODE_A=OUTREG,REGMODE_B=NOREG
DP8KC:REGMODE_A=OUTREG,REGMODE_B=OUTREG
DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL
DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE
DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH
PIO:IOTYPE=LVCMOS12
PIO:IOTYPE=LVCMOS15
PIO:IOTYPE=LVCMOS18
PIO:IOTYPE=LVCMOS25
PIO:IOTYPE=LVCMOS33
PIO:IOTYPE=LVDS
PIO:IOTYPE=SSTL15_I
PIO:IOTYPE=SSTL15_II
PIO:IOTYPE=SSTL18_I
PIO:IOTYPE=SSTL18_II
SLICE

DP8KC:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4979	4979	4979	4979	4979	4979
CLKA	DOA1	4979	4979	4979	4979	4979	4979
CLKA	DOA2	4979	4979	4979	4979	4979	4979
CLKA	DOA3	4979	4979	4979	4979	4979	4979
CLKA	DOA4	4979	4979	4979	4979	4979	4979
CLKA	DOA5	4979	4979	4979	4979	4979	4979
CLKA	DOA6	4979	4979	4979	4979	4979	4979
CLKA	DOA7	4979	4979	4979	4979	4979	4979
CLKA	DOA8	4979	4979	4979	4979	4979	4979
CLKB	DOB0	5224	5224	5224	5224	5224	5224
CLKB	DOB1	5224	5224	5224	5224	5224	5224
CLKB	DOB2	5224	5224	5224	5224	5224	5224
CLKB	DOB3	5224	5224	5224	5224	5224	5224
CLKB	DOB4	5224	5224	5224	5224	5224	5224
CLKB	DOB5	5224	5224	5224	5224	5224	5224
CLKB	DOB6	5224	5224	5224	5224	5224	5224
CLKB	DOB7	5224	5224	5224	5224	5224	5224
CLKB	DOB8	5224	5224	5224	5224	5224	5224

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	79	79	79
ADA1	posedge CLKA	0	0	0	79	79	79
ADA10	posedge CLKA	0	0	0	79	79	79
ADA11	posedge CLKA	0	0	0	79	79	79
ADA12	posedge CLKA	0	0	0	79	79	79
ADA2	posedge CLKA	0	0	0	79	79	79
ADA3	posedge CLKA	0	0	0	79	79	79
ADA4	posedge CLKA	0	0	0	79	79	79
ADA5	posedge CLKA	0	0	0	79	79	79
ADA6	posedge CLKA	0	0	0	79	79	79
ADA7	posedge CLKA	0	0	0	79	79	79
ADA8	posedge CLKA	0	0	0	79	79	79
ADA9	posedge CLKA	0	0	0	79	79	79
ADB0	posedge CLKB	0	0	0	184	184	184
ADB1	posedge CLKB	0	0	0	184	184	184
ADB10	posedge CLKB	0	0	0	184	184	184
ADB11	posedge CLKB	0	0	0	184	184	184
ADB12	posedge CLKB	0	0	0	184	184	184
ADB2	posedge CLKB	0	0	0	184	184	184
ADB3	posedge CLKB	0	0	0	184	184	184
ADB4	posedge CLKB	0	0	0	184	184	184
ADB5	posedge CLKB	0	0	0	184	184	184
ADB6	posedge CLKB	0	0	0	184	184	184
ADB7	posedge CLKB	0	0	0	184	184	184
ADB8	posedge CLKB	0	0	0	184	184	184
ADB9	posedge CLKB	0	0	0	184	184	184
CEA	posedge CLKA	226	226	226	0	0	0
CEB	posedge CLKB	250	250	250	0	0	0
CSA0	posedge CLKA	121	121	121	0	0	0
CSA1	posedge CLKA	121	121	121	0	0	0
CSA2	posedge CLKA	121	121	121	0	0	0
CSB0	posedge CLKB	0	0	0	90	90	90
CSB1	posedge CLKB	0	0	0	90	90	90
CSB2	posedge CLKB	0	0	0	90	90	90
DIA0	posedge CLKA	0	0	0	99	99	99
DIA1	posedge CLKA	0	0	0	99	99	99
DIA2	posedge CLKA	0	0	0	99	99	99
DIA3	posedge CLKA	0	0	0	99	99	99
DIA4	posedge CLKA	0	0	0	99	99	99
DIA5	posedge CLKA	0	0	0	99	99	99
DIA6	posedge CLKA	0	0	0	99	99	99
DIA7	posedge CLKA	0	0	0	99	99	99
DIA8	posedge CLKA	0	0	0	99	99	99
DIB0	posedge CLKB	0	0	0	190	190	190
DIB1	posedge CLKB	0	0	0	190	190	190
DIB2	posedge CLKB	0	0	0	190	190	190
DIB3	posedge CLKB	0	0	0	190	190	190
DIB4	posedge CLKB	0	0	0	190	190	190
DIB5	posedge CLKB	0	0	0	190	190	190
DIB6	posedge CLKB	0	0	0	190	190	190
DIB7	posedge CLKB	0	0	0	190	190	190
DIB8	posedge CLKB	0	0	0	190	190	190
OCEA	posedge CLKA	0	0	0	147	147	147
OCEB	posedge CLKB	0	0	0	183	183	183
RSTA	posedge CLKA	419	419	419	0	0	0
RSTB	posedge CLKB	136	136	136	43	43	43
WEA	posedge CLKA	128	128	128	0	0	0
WEB	posedge CLKB	12	12	12	44	44	44

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	3333	3333	3333	150	150	150
negedge CLKB	3333	3333	3333	150	150	150
posedge CLKA	3333	3333	3333	150	150	150
posedge CLKB	3333	3333	3333	150	150	150

DP8KC:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4979	4979	4979	4979	4979	4979
CLKA	DOA1	4979	4979	4979	4979	4979	4979
CLKA	DOA2	4979	4979	4979	4979	4979	4979
CLKA	DOA3	4979	4979	4979	4979	4979	4979
CLKA	DOA4	4979	4979	4979	4979	4979	4979
CLKA	DOA5	4979	4979	4979	4979	4979	4979
CLKA	DOA6	4979	4979	4979	4979	4979	4979
CLKA	DOA7	4979	4979	4979	4979	4979	4979
CLKA	DOA8	4979	4979	4979	4979	4979	4979
CLKB	DOB0	1016	1016	1016	1016	1016	1016
CLKB	DOB1	1016	1016	1016	1016	1016	1016
CLKB	DOB2	1016	1016	1016	1016	1016	1016
CLKB	DOB3	1016	1016	1016	1016	1016	1016
CLKB	DOB4	1016	1016	1016	1016	1016	1016
CLKB	DOB5	1016	1016	1016	1016	1016	1016
CLKB	DOB6	1016	1016	1016	1016	1016	1016
CLKB	DOB7	1016	1016	1016	1016	1016	1016
CLKB	DOB8	1016	1016	1016	1016	1016	1016

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	79	79	79
ADA1	posedge CLKA	0	0	0	79	79	79
ADA10	posedge CLKA	0	0	0	79	79	79
ADA11	posedge CLKA	0	0	0	79	79	79
ADA12	posedge CLKA	0	0	0	79	79	79
ADA2	posedge CLKA	0	0	0	79	79	79
ADA3	posedge CLKA	0	0	0	79	79	79
ADA4	posedge CLKA	0	0	0	79	79	79
ADA5	posedge CLKA	0	0	0	79	79	79
ADA6	posedge CLKA	0	0	0	79	79	79
ADA7	posedge CLKA	0	0	0	79	79	79
ADA8	posedge CLKA	0	0	0	79	79	79
ADA9	posedge CLKA	0	0	0	79	79	79
ADB0	posedge CLKB	0	0	0	184	184	184
ADB1	posedge CLKB	0	0	0	184	184	184
ADB10	posedge CLKB	0	0	0	184	184	184
ADB11	posedge CLKB	0	0	0	184	184	184
ADB12	posedge CLKB	0	0	0	184	184	184
ADB2	posedge CLKB	0	0	0	184	184	184
ADB3	posedge CLKB	0	0	0	184	184	184
ADB4	posedge CLKB	0	0	0	184	184	184
ADB5	posedge CLKB	0	0	0	184	184	184
ADB6	posedge CLKB	0	0	0	184	184	184
ADB7	posedge CLKB	0	0	0	184	184	184
ADB8	posedge CLKB	0	0	0	184	184	184
ADB9	posedge CLKB	0	0	0	184	184	184
CEA	posedge CLKA	226	226	226	0	0	0
CEB	posedge CLKB	250	250	250	0	0	0
CSA0	posedge CLKA	121	121	121	0	0	0
CSA1	posedge CLKA	121	121	121	0	0	0
CSA2	posedge CLKA	121	121	121	0	0	0
CSB0	posedge CLKB	0	0	0	90	90	90
CSB1	posedge CLKB	0	0	0	90	90	90
CSB2	posedge CLKB	0	0	0	90	90	90
DIA0	posedge CLKA	0	0	0	99	99	99
DIA1	posedge CLKA	0	0	0	99	99	99
DIA2	posedge CLKA	0	0	0	99	99	99
DIA3	posedge CLKA	0	0	0	99	99	99
DIA4	posedge CLKA	0	0	0	99	99	99
DIA5	posedge CLKA	0	0	0	99	99	99
DIA6	posedge CLKA	0	0	0	99	99	99
DIA7	posedge CLKA	0	0	0	99	99	99
DIA8	posedge CLKA	0	0	0	99	99	99
DIB0	posedge CLKB	0	0	0	190	190	190
DIB1	posedge CLKB	0	0	0	190	190	190
DIB2	posedge CLKB	0	0	0	190	190	190
DIB3	posedge CLKB	0	0	0	190	190	190
DIB4	posedge CLKB	0	0	0	190	190	190
DIB5	posedge CLKB	0	0	0	190	190	190
DIB6	posedge CLKB	0	0	0	190	190	190
DIB7	posedge CLKB	0	0	0	190	190	190
DIB8	posedge CLKB	0	0	0	190	190	190
OCEA	posedge CLKA	0	0	0	147	147	147
OCEB	posedge CLKB	0	0	0	183	183	183
RSTA	posedge CLKA	419	419	419	0	0	0
RSTB	posedge CLKB	249	249	249	43	43	43
WEA	posedge CLKA	128	128	128	0	0	0
WEB	posedge CLKB	12	12	12	44	44	44

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	3333	3333	3333	150	150	150
negedge CLKB	3333	3333	3333	150	150	150
posedge CLKA	3333	3333	3333	150	150	150
posedge CLKB	3333	3333	3333	150	150	150

DP8KC:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	979	979	979	979	979	979
CLKA	DOA1	979	979	979	979	979	979
CLKA	DOA2	979	979	979	979	979	979
CLKA	DOA3	979	979	979	979	979	979
CLKA	DOA4	979	979	979	979	979	979
CLKA	DOA5	979	979	979	979	979	979
CLKA	DOA6	979	979	979	979	979	979
CLKA	DOA7	979	979	979	979	979	979
CLKA	DOA8	979	979	979	979	979	979
CLKB	DOB0	5224	5224	5224	5224	5224	5224
CLKB	DOB1	5224	5224	5224	5224	5224	5224
CLKB	DOB2	5224	5224	5224	5224	5224	5224
CLKB	DOB3	5224	5224	5224	5224	5224	5224
CLKB	DOB4	5224	5224	5224	5224	5224	5224
CLKB	DOB5	5224	5224	5224	5224	5224	5224
CLKB	DOB6	5224	5224	5224	5224	5224	5224
CLKB	DOB7	5224	5224	5224	5224	5224	5224
CLKB	DOB8	5224	5224	5224	5224	5224	5224

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	79	79	79
ADA1	posedge CLKA	0	0	0	79	79	79
ADA10	posedge CLKA	0	0	0	79	79	79
ADA11	posedge CLKA	0	0	0	79	79	79
ADA12	posedge CLKA	0	0	0	79	79	79
ADA2	posedge CLKA	0	0	0	79	79	79
ADA3	posedge CLKA	0	0	0	79	79	79
ADA4	posedge CLKA	0	0	0	79	79	79
ADA5	posedge CLKA	0	0	0	79	79	79
ADA6	posedge CLKA	0	0	0	79	79	79
ADA7	posedge CLKA	0	0	0	79	79	79
ADA8	posedge CLKA	0	0	0	79	79	79
ADA9	posedge CLKA	0	0	0	79	79	79
ADB0	posedge CLKB	0	0	0	184	184	184
ADB1	posedge CLKB	0	0	0	184	184	184
ADB10	posedge CLKB	0	0	0	184	184	184
ADB11	posedge CLKB	0	0	0	184	184	184
ADB12	posedge CLKB	0	0	0	184	184	184
ADB2	posedge CLKB	0	0	0	184	184	184
ADB3	posedge CLKB	0	0	0	184	184	184
ADB4	posedge CLKB	0	0	0	184	184	184
ADB5	posedge CLKB	0	0	0	184	184	184
ADB6	posedge CLKB	0	0	0	184	184	184
ADB7	posedge CLKB	0	0	0	184	184	184
ADB8	posedge CLKB	0	0	0	184	184	184
ADB9	posedge CLKB	0	0	0	184	184	184
CEA	posedge CLKA	226	226	226	0	0	0
CEB	posedge CLKB	250	250	250	0	0	0
CSA0	posedge CLKA	121	121	121	0	0	0
CSA1	posedge CLKA	121	121	121	0	0	0
CSA2	posedge CLKA	121	121	121	0	0	0
CSB0	posedge CLKB	0	0	0	90	90	90
CSB1	posedge CLKB	0	0	0	90	90	90
CSB2	posedge CLKB	0	0	0	90	90	90
DIA0	posedge CLKA	0	0	0	99	99	99
DIA1	posedge CLKA	0	0	0	99	99	99
DIA2	posedge CLKA	0	0	0	99	99	99
DIA3	posedge CLKA	0	0	0	99	99	99
DIA4	posedge CLKA	0	0	0	99	99	99
DIA5	posedge CLKA	0	0	0	99	99	99
DIA6	posedge CLKA	0	0	0	99	99	99
DIA7	posedge CLKA	0	0	0	99	99	99
DIA8	posedge CLKA	0	0	0	99	99	99
DIB0	posedge CLKB	0	0	0	190	190	190
DIB1	posedge CLKB	0	0	0	190	190	190
DIB2	posedge CLKB	0	0	0	190	190	190
DIB3	posedge CLKB	0	0	0	190	190	190
DIB4	posedge CLKB	0	0	0	190	190	190
DIB5	posedge CLKB	0	0	0	190	190	190
DIB6	posedge CLKB	0	0	0	190	190	190
DIB7	posedge CLKB	0	0	0	190	190	190
DIB8	posedge CLKB	0	0	0	190	190	190
OCEA	posedge CLKA	0	0	0	147	147	147
OCEB	posedge CLKB	0	0	0	183	183	183
RSTA	posedge CLKA	419	419	419	0	0	0
RSTB	posedge CLKB	136	136	136	43	43	43
WEA	posedge CLKA	128	128	128	0	0	0
WEB	posedge CLKB	12	12	12	44	44	44

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	3333	3333	3333	150	150	150
negedge CLKB	3333	3333	3333	150	150	150
posedge CLKA	3333	3333	3333	150	150	150
posedge CLKB	3333	3333	3333	150	150	150

DP8KC:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	979	979	979	979	979	979
CLKA	DOA1	979	979	979	979	979	979
CLKA	DOA2	979	979	979	979	979	979
CLKA	DOA3	979	979	979	979	979	979
CLKA	DOA4	979	979	979	979	979	979
CLKA	DOA5	979	979	979	979	979	979
CLKA	DOA6	979	979	979	979	979	979
CLKA	DOA7	979	979	979	979	979	979
CLKA	DOA8	979	979	979	979	979	979
CLKB	DOB0	1016	1016	1016	1016	1016	1016
CLKB	DOB1	1016	1016	1016	1016	1016	1016
CLKB	DOB2	1016	1016	1016	1016	1016	1016
CLKB	DOB3	1016	1016	1016	1016	1016	1016
CLKB	DOB4	1016	1016	1016	1016	1016	1016
CLKB	DOB5	1016	1016	1016	1016	1016	1016
CLKB	DOB6	1016	1016	1016	1016	1016	1016
CLKB	DOB7	1016	1016	1016	1016	1016	1016
CLKB	DOB8	1016	1016	1016	1016	1016	1016

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	79	79	79
ADA1	posedge CLKA	0	0	0	79	79	79
ADA10	posedge CLKA	0	0	0	79	79	79
ADA11	posedge CLKA	0	0	0	79	79	79
ADA12	posedge CLKA	0	0	0	79	79	79
ADA2	posedge CLKA	0	0	0	79	79	79
ADA3	posedge CLKA	0	0	0	79	79	79
ADA4	posedge CLKA	0	0	0	79	79	79
ADA5	posedge CLKA	0	0	0	79	79	79
ADA6	posedge CLKA	0	0	0	79	79	79
ADA7	posedge CLKA	0	0	0	79	79	79
ADA8	posedge CLKA	0	0	0	79	79	79
ADA9	posedge CLKA	0	0	0	79	79	79
ADB0	posedge CLKB	0	0	0	184	184	184
ADB1	posedge CLKB	0	0	0	184	184	184
ADB10	posedge CLKB	0	0	0	184	184	184
ADB11	posedge CLKB	0	0	0	184	184	184
ADB12	posedge CLKB	0	0	0	184	184	184
ADB2	posedge CLKB	0	0	0	184	184	184
ADB3	posedge CLKB	0	0	0	184	184	184
ADB4	posedge CLKB	0	0	0	184	184	184
ADB5	posedge CLKB	0	0	0	184	184	184
ADB6	posedge CLKB	0	0	0	184	184	184
ADB7	posedge CLKB	0	0	0	184	184	184
ADB8	posedge CLKB	0	0	0	184	184	184
ADB9	posedge CLKB	0	0	0	184	184	184
CEA	posedge CLKA	226	226	226	0	0	0
CEB	posedge CLKB	250	250	250	0	0	0
CSA0	posedge CLKA	121	121	121	0	0	0
CSA1	posedge CLKA	121	121	121	0	0	0
CSA2	posedge CLKA	121	121	121	0	0	0
CSB0	posedge CLKB	0	0	0	90	90	90
CSB1	posedge CLKB	0	0	0	90	90	90
CSB2	posedge CLKB	0	0	0	90	90	90
DIA0	posedge CLKA	0	0	0	99	99	99
DIA1	posedge CLKA	0	0	0	99	99	99
DIA2	posedge CLKA	0	0	0	99	99	99
DIA3	posedge CLKA	0	0	0	99	99	99
DIA4	posedge CLKA	0	0	0	99	99	99
DIA5	posedge CLKA	0	0	0	99	99	99
DIA6	posedge CLKA	0	0	0	99	99	99
DIA7	posedge CLKA	0	0	0	99	99	99
DIA8	posedge CLKA	0	0	0	99	99	99
DIB0	posedge CLKB	0	0	0	190	190	190
DIB1	posedge CLKB	0	0	0	190	190	190
DIB2	posedge CLKB	0	0	0	190	190	190
DIB3	posedge CLKB	0	0	0	190	190	190
DIB4	posedge CLKB	0	0	0	190	190	190
DIB5	posedge CLKB	0	0	0	190	190	190
DIB6	posedge CLKB	0	0	0	190	190	190
DIB7	posedge CLKB	0	0	0	190	190	190
DIB8	posedge CLKB	0	0	0	190	190	190
OCEA	posedge CLKA	0	0	0	147	147	147
OCEB	posedge CLKB	0	0	0	183	183	183
RSTA	posedge CLKA	419	419	419	0	0	0
RSTB	posedge CLKB	249	249	249	43	43	43
WEA	posedge CLKA	128	128	128	0	0	0
WEB	posedge CLKB	12	12	12	44	44	44

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	3333	3333	3333	150	150	150
negedge CLKB	3333	3333	3333	150	150	150
posedge CLKA	3333	3333	3333	150	150	150
posedge CLKB	3333	3333	3333	150	150	150

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4979	4979	4979	4979	4979	4979
CLKA	DOA1	4979	4979	4979	4979	4979	4979
CLKA	DOA2	4979	4979	4979	4979	4979	4979
CLKA	DOA3	4979	4979	4979	4979	4979	4979
CLKA	DOA4	4979	4979	4979	4979	4979	4979
CLKA	DOA5	4979	4979	4979	4979	4979	4979
CLKA	DOA6	4979	4979	4979	4979	4979	4979
CLKA	DOA7	4979	4979	4979	4979	4979	4979
CLKA	DOA8	4979	4979	4979	4979	4979	4979
CLKB	DOB0	5224	5224	5224	5224	5224	5224
CLKB	DOB1	5224	5224	5224	5224	5224	5224
CLKB	DOB2	5224	5224	5224	5224	5224	5224
CLKB	DOB3	5224	5224	5224	5224	5224	5224
CLKB	DOB4	5224	5224	5224	5224	5224	5224
CLKB	DOB5	5224	5224	5224	5224	5224	5224
CLKB	DOB6	5224	5224	5224	5224	5224	5224
CLKB	DOB7	5224	5224	5224	5224	5224	5224
CLKB	DOB8	5224	5224	5224	5224	5224	5224

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	79	79	79
ADA1	posedge CLKA	0	0	0	79	79	79
ADA10	posedge CLKA	0	0	0	79	79	79
ADA11	posedge CLKA	0	0	0	79	79	79
ADA12	posedge CLKA	0	0	0	79	79	79
ADA2	posedge CLKA	0	0	0	79	79	79
ADA3	posedge CLKA	0	0	0	79	79	79
ADA4	posedge CLKA	0	0	0	79	79	79
ADA5	posedge CLKA	0	0	0	79	79	79
ADA6	posedge CLKA	0	0	0	79	79	79
ADA7	posedge CLKA	0	0	0	79	79	79
ADA8	posedge CLKA	0	0	0	79	79	79
ADA9	posedge CLKA	0	0	0	79	79	79
ADB0	posedge CLKB	0	0	0	184	184	184
ADB1	posedge CLKB	0	0	0	184	184	184
ADB10	posedge CLKB	0	0	0	184	184	184
ADB11	posedge CLKB	0	0	0	184	184	184
ADB12	posedge CLKB	0	0	0	184	184	184
ADB2	posedge CLKB	0	0	0	184	184	184
ADB3	posedge CLKB	0	0	0	184	184	184
ADB4	posedge CLKB	0	0	0	184	184	184
ADB5	posedge CLKB	0	0	0	184	184	184
ADB6	posedge CLKB	0	0	0	184	184	184
ADB7	posedge CLKB	0	0	0	184	184	184
ADB8	posedge CLKB	0	0	0	184	184	184
ADB9	posedge CLKB	0	0	0	184	184	184
CEA	posedge CLKA	226	226	226	0	0	0
CEB	posedge CLKB	250	250	250	0	0	0
CSA0	posedge CLKA	121	121	121	0	0	0
CSA1	posedge CLKA	121	121	121	0	0	0
CSA2	posedge CLKA	121	121	121	0	0	0
CSB0	posedge CLKB	0	0	0	90	90	90
CSB1	posedge CLKB	0	0	0	90	90	90
CSB2	posedge CLKB	0	0	0	90	90	90
DIA0	posedge CLKA	0	0	0	99	99	99
DIA1	posedge CLKA	0	0	0	99	99	99
DIA2	posedge CLKA	0	0	0	99	99	99
DIA3	posedge CLKA	0	0	0	99	99	99
DIA4	posedge CLKA	0	0	0	99	99	99
DIA5	posedge CLKA	0	0	0	99	99	99
DIA6	posedge CLKA	0	0	0	99	99	99
DIA7	posedge CLKA	0	0	0	99	99	99
DIA8	posedge CLKA	0	0	0	99	99	99
DIB0	posedge CLKB	0	0	0	190	190	190
DIB1	posedge CLKB	0	0	0	190	190	190
DIB2	posedge CLKB	0	0	0	190	190	190
DIB3	posedge CLKB	0	0	0	190	190	190
DIB4	posedge CLKB	0	0	0	190	190	190
DIB5	posedge CLKB	0	0	0	190	190	190
DIB6	posedge CLKB	0	0	0	190	190	190
DIB7	posedge CLKB	0	0	0	190	190	190
DIB8	posedge CLKB	0	0	0	190	190	190
OCEA	posedge CLKA	0	0	0	147	147	147
OCEB	posedge CLKB	0	0	0	183	183	183
RSTA	posedge CLKA	419	419	419	0	0	0
RSTB	posedge CLKB	136	136	136	43	43	43
WEA	posedge CLKA	128	128	128	0	0	0
WEB	posedge CLKB	12	12	12	44	44	44

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	3333	3333	3333	150	150	150
negedge CLKB	3333	3333	3333	150	150	150
posedge CLKA	3333	3333	3333	150	150	150
posedge CLKB	3333	3333	3333	150	150	150

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4979	4979	4979	4979	4979	4979
CLKA	DOA1	4979	4979	4979	4979	4979	4979
CLKA	DOA2	4979	4979	4979	4979	4979	4979
CLKA	DOA3	4979	4979	4979	4979	4979	4979
CLKA	DOA4	4979	4979	4979	4979	4979	4979
CLKA	DOA5	4979	4979	4979	4979	4979	4979
CLKA	DOA6	4979	4979	4979	4979	4979	4979
CLKA	DOA7	4979	4979	4979	4979	4979	4979
CLKA	DOA8	4979	4979	4979	4979	4979	4979
CLKB	DOB0	5224	5224	5224	5224	5224	5224
CLKB	DOB1	5224	5224	5224	5224	5224	5224
CLKB	DOB2	5224	5224	5224	5224	5224	5224
CLKB	DOB3	5224	5224	5224	5224	5224	5224
CLKB	DOB4	5224	5224	5224	5224	5224	5224
CLKB	DOB5	5224	5224	5224	5224	5224	5224
CLKB	DOB6	5224	5224	5224	5224	5224	5224
CLKB	DOB7	5224	5224	5224	5224	5224	5224
CLKB	DOB8	5224	5224	5224	5224	5224	5224

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	79	79	79
ADA1	posedge CLKA	0	0	0	79	79	79
ADA10	posedge CLKA	0	0	0	79	79	79
ADA11	posedge CLKA	0	0	0	79	79	79
ADA12	posedge CLKA	0	0	0	79	79	79
ADA2	posedge CLKA	0	0	0	79	79	79
ADA3	posedge CLKA	0	0	0	79	79	79
ADA4	posedge CLKA	0	0	0	79	79	79
ADA5	posedge CLKA	0	0	0	79	79	79
ADA6	posedge CLKA	0	0	0	79	79	79
ADA7	posedge CLKA	0	0	0	79	79	79
ADA8	posedge CLKA	0	0	0	79	79	79
ADA9	posedge CLKA	0	0	0	79	79	79
ADB0	posedge CLKB	0	0	0	184	184	184
ADB1	posedge CLKB	0	0	0	184	184	184
ADB10	posedge CLKB	0	0	0	184	184	184
ADB11	posedge CLKB	0	0	0	184	184	184
ADB12	posedge CLKB	0	0	0	184	184	184
ADB2	posedge CLKB	0	0	0	184	184	184
ADB3	posedge CLKB	0	0	0	184	184	184
ADB4	posedge CLKB	0	0	0	184	184	184
ADB5	posedge CLKB	0	0	0	184	184	184
ADB6	posedge CLKB	0	0	0	184	184	184
ADB7	posedge CLKB	0	0	0	184	184	184
ADB8	posedge CLKB	0	0	0	184	184	184
ADB9	posedge CLKB	0	0	0	184	184	184
CEA	posedge CLKA	226	226	226	0	0	0
CEB	posedge CLKB	250	250	250	0	0	0
CSA0	posedge CLKA	121	121	121	0	0	0
CSA1	posedge CLKA	121	121	121	0	0	0
CSA2	posedge CLKA	121	121	121	0	0	0
CSB0	posedge CLKB	0	0	0	90	90	90
CSB1	posedge CLKB	0	0	0	90	90	90
CSB2	posedge CLKB	0	0	0	90	90	90
DIA0	posedge CLKA	0	0	0	99	99	99
DIA1	posedge CLKA	0	0	0	99	99	99
DIA2	posedge CLKA	0	0	0	99	99	99
DIA3	posedge CLKA	0	0	0	99	99	99
DIA4	posedge CLKA	0	0	0	99	99	99
DIA5	posedge CLKA	0	0	0	99	99	99
DIA6	posedge CLKA	0	0	0	99	99	99
DIA7	posedge CLKA	0	0	0	99	99	99
DIA8	posedge CLKA	0	0	0	99	99	99
DIB0	posedge CLKB	0	0	0	190	190	190
DIB1	posedge CLKB	0	0	0	190	190	190
DIB2	posedge CLKB	0	0	0	190	190	190
DIB3	posedge CLKB	0	0	0	190	190	190
DIB4	posedge CLKB	0	0	0	190	190	190
DIB5	posedge CLKB	0	0	0	190	190	190
DIB6	posedge CLKB	0	0	0	190	190	190
DIB7	posedge CLKB	0	0	0	190	190	190
DIB8	posedge CLKB	0	0	0	190	190	190
OCEA	posedge CLKA	0	0	0	147	147	147
OCEB	posedge CLKB	0	0	0	183	183	183
RSTA	posedge CLKA	419	419	419	0	0	0
RSTB	posedge CLKB	136	136	136	43	43	43
WEA	posedge CLKA	128	128	128	0	0	0
WEB	posedge CLKB	12	12	12	44	44	44

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	3333	3333	3333	150	150	150
negedge CLKB	5080	5080	5080	98	98	98
posedge CLKA	3333	3333	3333	150	150	150
posedge CLKB	5080	5080	5080	98	98	98

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4979	4979	4979	4979	4979	4979
CLKA	DOA1	4979	4979	4979	4979	4979	4979
CLKA	DOA2	4979	4979	4979	4979	4979	4979
CLKA	DOA3	4979	4979	4979	4979	4979	4979
CLKA	DOA4	4979	4979	4979	4979	4979	4979
CLKA	DOA5	4979	4979	4979	4979	4979	4979
CLKA	DOA6	4979	4979	4979	4979	4979	4979
CLKA	DOA7	4979	4979	4979	4979	4979	4979
CLKA	DOA8	4979	4979	4979	4979	4979	4979
CLKB	DOB0	5224	5224	5224	5224	5224	5224
CLKB	DOB1	5224	5224	5224	5224	5224	5224
CLKB	DOB2	5224	5224	5224	5224	5224	5224
CLKB	DOB3	5224	5224	5224	5224	5224	5224
CLKB	DOB4	5224	5224	5224	5224	5224	5224
CLKB	DOB5	5224	5224	5224	5224	5224	5224
CLKB	DOB6	5224	5224	5224	5224	5224	5224
CLKB	DOB7	5224	5224	5224	5224	5224	5224
CLKB	DOB8	5224	5224	5224	5224	5224	5224

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	79	79	79
ADA1	posedge CLKA	0	0	0	79	79	79
ADA10	posedge CLKA	0	0	0	79	79	79
ADA11	posedge CLKA	0	0	0	79	79	79
ADA12	posedge CLKA	0	0	0	79	79	79
ADA2	posedge CLKA	0	0	0	79	79	79
ADA3	posedge CLKA	0	0	0	79	79	79
ADA4	posedge CLKA	0	0	0	79	79	79
ADA5	posedge CLKA	0	0	0	79	79	79
ADA6	posedge CLKA	0	0	0	79	79	79
ADA7	posedge CLKA	0	0	0	79	79	79
ADA8	posedge CLKA	0	0	0	79	79	79
ADA9	posedge CLKA	0	0	0	79	79	79
ADB0	posedge CLKB	0	0	0	184	184	184
ADB1	posedge CLKB	0	0	0	184	184	184
ADB10	posedge CLKB	0	0	0	184	184	184
ADB11	posedge CLKB	0	0	0	184	184	184
ADB12	posedge CLKB	0	0	0	184	184	184
ADB2	posedge CLKB	0	0	0	184	184	184
ADB3	posedge CLKB	0	0	0	184	184	184
ADB4	posedge CLKB	0	0	0	184	184	184
ADB5	posedge CLKB	0	0	0	184	184	184
ADB6	posedge CLKB	0	0	0	184	184	184
ADB7	posedge CLKB	0	0	0	184	184	184
ADB8	posedge CLKB	0	0	0	184	184	184
ADB9	posedge CLKB	0	0	0	184	184	184
CEA	posedge CLKA	226	226	226	0	0	0
CEB	posedge CLKB	250	250	250	0	0	0
CSA0	posedge CLKA	121	121	121	0	0	0
CSA1	posedge CLKA	121	121	121	0	0	0
CSA2	posedge CLKA	121	121	121	0	0	0
CSB0	posedge CLKB	0	0	0	90	90	90
CSB1	posedge CLKB	0	0	0	90	90	90
CSB2	posedge CLKB	0	0	0	90	90	90
DIA0	posedge CLKA	0	0	0	99	99	99
DIA1	posedge CLKA	0	0	0	99	99	99
DIA2	posedge CLKA	0	0	0	99	99	99
DIA3	posedge CLKA	0	0	0	99	99	99
DIA4	posedge CLKA	0	0	0	99	99	99
DIA5	posedge CLKA	0	0	0	99	99	99
DIA6	posedge CLKA	0	0	0	99	99	99
DIA7	posedge CLKA	0	0	0	99	99	99
DIA8	posedge CLKA	0	0	0	99	99	99
DIB0	posedge CLKB	0	0	0	190	190	190
DIB1	posedge CLKB	0	0	0	190	190	190
DIB2	posedge CLKB	0	0	0	190	190	190
DIB3	posedge CLKB	0	0	0	190	190	190
DIB4	posedge CLKB	0	0	0	190	190	190
DIB5	posedge CLKB	0	0	0	190	190	190
DIB6	posedge CLKB	0	0	0	190	190	190
DIB7	posedge CLKB	0	0	0	190	190	190
DIB8	posedge CLKB	0	0	0	190	190	190
OCEA	posedge CLKA	0	0	0	147	147	147
OCEB	posedge CLKB	0	0	0	183	183	183
RSTA	posedge CLKA	419	419	419	0	0	0
RSTB	posedge CLKB	136	136	136	43	43	43
WEA	posedge CLKA	128	128	128	0	0	0
WEB	posedge CLKB	12	12	12	44	44	44

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	3333	3333	3333	150	150	150
negedge CLKB	3333	3333	3333	150	150	150
posedge CLKA	3333	3333	3333	150	150	150
posedge CLKB	3333	3333	3333	150	150	150

PIO:IOTYPE=LVCMOS12

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1037	1176	1315	1037	1176	1315
PADDO	PAD	7624	7699	7774	7624	7699	7774
PADDT	PAD	4397	8598	12800	4397	8598	12800

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	5500	5500	5500	91	91	91
posedge PAD	5500	5500	5500	91	91	91

PIO:IOTYPE=LVCMOS15

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	2298	2340	2383	2298	2340	2383
PADDO	PAD	4875	5041	5207	4875	5041	5207
PADDT	PAD	3221	5476	7732	3221	5476	7732

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVCMOS18

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1740	1753	1767	1740	1753	1767
PADDO	PAD	3735	3891	4048	3735	3891	4048
PADDT	PAD	2742	4200	5658	2742	4200	5658

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVCMOS25

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1223	1297	1372	1223	1297	1372
PADDO	PAD	3220	3334	3448	3220	3334	3448
PADDT	PAD	2349	3502	4656	2349	3502	4656

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVCMOS33

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1007	1069	1132	1007	1069	1132
PADDO	PAD	2611	2704	2797	2611	2704	2797
PADDT	PAD	2387	3283	4180	2387	3283	4180

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVDS

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1087	1105	1123	1087	1105	1123
PADDO	PAD	2803	2803	2804	2803	2803	2804
PADDT	PAD	2906	4040	5174	2906	4040	5174

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL15_I

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1087	1105	1123	1087	1105	1123
PADDO	PAD	2803	2803	2804	2803	2803	2804
PADDT	PAD	2906	4040	5174	2906	4040	5174

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL15_II

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1087	1105	1123	1087	1105	1123
PADDO	PAD	2803	2803	2804	2803	2803	2804
PADDT	PAD	2906	4040	5174	2906	4040	5174

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL18_I

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1282	1330	1378	1282	1330	1378
PADDO	PAD	3136	3311	3486	3136	3311	3486
PADDT	PAD	3754	4790	5827	3754	4790	5827

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL18_II

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1087	1105	1123	1087	1105	1123
PADDO	PAD	2803	2803	2804	2803	2803	2804
PADDT	PAD	2906	4040	5174	2906	4040	5174

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

SLICE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A0	F0	367	431	495	367	431	495
A0	F1	718	803	889	718	803	889
A0	FCO	827	925	1023	827	925	1023
A0	OFX0	457	589	721	457	589	721
A1	F1	367	431	495	367	431	495
A1	FCO	718	803	889	718	803	889
A1	OFX0	457	589	721	457	589	721
B0	F0	367	431	495	367	431	495
B0	F1	718	803	889	718	803	889
B0	FCO	827	925	1023	827	925	1023
B0	OFX0	457	589	721	457	589	721
B1	F1	367	431	495	367	431	495
B1	FCO	718	803	889	718	803	889
B1	OFX0	457	589	721	457	589	721
C0	F0	367	431	495	367	431	495
C0	F1	718	803	889	718	803	889
C0	FCO	827	925	1023	827	925	1023
C0	OFX0	457	589	721	457	589	721
C1	F1	367	431	495	367	431	495
C1	FCO	718	803	889	718	803	889
C1	OFX0	457	589	721	457	589	721
CLK	Q0	392	422	452	392	422	452
CLK	Q1	392	422	452	392	422	452
D0	F0	367	431	495	367	431	495
D0	F1	718	803	889	718	803	889
D0	FCO	827	925	1023	827	925	1023
D0	OFX0	457	589	721	457	589	721
D1	F1	367	431	495	367	431	495
D1	FCO	718	803	889	718	803	889
D1	OFX0	457	589	721	457	589	721
FCI	F0	473	529	585	473	529	585
FCI	F1	519	581	643	519	581	643
FCI	FCO	130	146	162	130	146	162
FXA	OFX1	199	220	241	199	220	241
FXB	OFX1	199	220	241	199	220	241
LSR	Q0	770	860	951	770	860	951
M0	OFX0	322	349	376	322	349	376
M1	OFX1	322	349	376	322	349	376
WCK	F0	1066	1232	1398	1066	1232	1398
WCK	F1	1066	1232	1398	1066	1232	1398

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	negedge CLK	247	277	307	0	0	0
CE	posedge CLK	229	255	282	0	0	0
DI0	negedge CLK	130	148	166	0	0	0
DI0	posedge CLK	130	148	166	0	0	0
DI1	posedge CLK	130	148	166	0	0	0
LSR	negedge CLK	236	260	285	0	0	0
LSR	posedge CLK	225	249	274	0	0	0
LSR	posedge CLK	733	733	733	0	0	0
M0	posedge CLK	256	302	348	0	0	0
M1	negedge CLK	256	302	348	0	0	0
M1	posedge CLK	256	302	348	0	0	0
WAD0	posedge WCK	0	0	0	491	519	548
WAD1	posedge WCK	0	0	0	491	519	548
WAD2	posedge WCK	0	0	0	491	519	548
WAD3	posedge WCK	0	0	0	491	519	548
WD0	posedge WCK	0	0	0	498	525	553
WD1	posedge WCK	0	0	0	498	525	553
WRE	posedge WCK	80	94	108	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1250	1250	1250	400	400	400
negedge LSR	4000	4000	4000	125	125	125
negedge WCK	1250	1250	1250	400	400	400
posedge CLK	1250	1250	1250	400	400	400
posedge LSR	4000	4000	4000	125	125	125
posedge WCK	1250	1250	1250	400	400	400

MachXO2 Speed Grade -4 Cell Timings

Contents

DP8KC:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

Setup/Hold Checks

Width Checks

PIO:IOTYPE=LVCMOS12

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS15

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS18

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS25

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS33

Propagation Delays

Width Checks

PIO:IOTYPE=LVDS

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL15_I

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL15_II

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL18_I

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL18_II

Propagation Delays

Width Checks

SLICE

Propagation Delays

Setup/Hold Checks

Width Checks