MachXO2 Speed Grade -6 Cell Timings

DP8KC:REGMODE_A=NOREG,REGMODE_B=NOREG
DP8KC:REGMODE_A=NOREG,REGMODE_B=OUTREG
DP8KC:REGMODE_A=OUTREG,REGMODE_B=NOREG
DP8KC:REGMODE_A=OUTREG,REGMODE_B=OUTREG
DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL
DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE
DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH
PIO:IOTYPE=LVCMOS12
PIO:IOTYPE=LVCMOS15
PIO:IOTYPE=LVCMOS18
PIO:IOTYPE=LVCMOS25
PIO:IOTYPE=LVCMOS33
PIO:IOTYPE=LVDS
PIO:IOTYPE=SSTL15_I
PIO:IOTYPE=SSTL15_II
PIO:IOTYPE=SSTL18_I
PIO:IOTYPE=SSTL18_II
SLICE

DP8KC:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4057	4057	4057	4057	4057	4057
CLKA	DOA1	4057	4057	4057	4057	4057	4057
CLKA	DOA2	4057	4057	4057	4057	4057	4057
CLKA	DOA3	4057	4057	4057	4057	4057	4057
CLKA	DOA4	4057	4057	4057	4057	4057	4057
CLKA	DOA5	4057	4057	4057	4057	4057	4057
CLKA	DOA6	4057	4057	4057	4057	4057	4057
CLKA	DOA7	4057	4057	4057	4057	4057	4057
CLKA	DOA8	4057	4057	4057	4057	4057	4057
CLKB	DOB0	4254	4254	4254	4254	4254	4254
CLKB	DOB1	4254	4254	4254	4254	4254	4254
CLKB	DOB2	4254	4254	4254	4254	4254	4254
CLKB	DOB3	4254	4254	4254	4254	4254	4254
CLKB	DOB4	4254	4254	4254	4254	4254	4254
CLKB	DOB5	4254	4254	4254	4254	4254	4254
CLKB	DOB6	4254	4254	4254	4254	4254	4254
CLKB	DOB7	4254	4254	4254	4254	4254	4254
CLKB	DOB8	4254	4254	4254	4254	4254	4254

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	75	75	75
ADA1	posedge CLKA	0	0	0	75	75	75
ADA10	posedge CLKA	0	0	0	75	75	75
ADA11	posedge CLKA	0	0	0	75	75	75
ADA12	posedge CLKA	0	0	0	75	75	75
ADA2	posedge CLKA	0	0	0	75	75	75
ADA3	posedge CLKA	0	0	0	75	75	75
ADA4	posedge CLKA	0	0	0	75	75	75
ADA5	posedge CLKA	0	0	0	75	75	75
ADA6	posedge CLKA	0	0	0	75	75	75
ADA7	posedge CLKA	0	0	0	75	75	75
ADA8	posedge CLKA	0	0	0	75	75	75
ADA9	posedge CLKA	0	0	0	75	75	75
ADB0	posedge CLKB	0	0	0	154	154	154
ADB1	posedge CLKB	0	0	0	154	154	154
ADB10	posedge CLKB	0	0	0	154	154	154
ADB11	posedge CLKB	0	0	0	154	154	154
ADB12	posedge CLKB	0	0	0	154	154	154
ADB2	posedge CLKB	0	0	0	154	154	154
ADB3	posedge CLKB	0	0	0	154	154	154
ADB4	posedge CLKB	0	0	0	154	154	154
ADB5	posedge CLKB	0	0	0	154	154	154
ADB6	posedge CLKB	0	0	0	154	154	154
ADB7	posedge CLKB	0	0	0	154	154	154
ADB8	posedge CLKB	0	0	0	154	154	154
ADB9	posedge CLKB	0	0	0	154	154	154
CEA	posedge CLKA	174	174	174	0	0	0
CEB	posedge CLKB	187	187	187	0	0	0
CSA0	posedge CLKA	116	116	116	0	0	0
CSA1	posedge CLKA	116	116	116	0	0	0
CSA2	posedge CLKA	116	116	116	0	0	0
CSB0	posedge CLKB	8	8	8	83	83	83
CSB1	posedge CLKB	8	8	8	83	83	83
CSB2	posedge CLKB	8	8	8	83	83	83
DIA0	posedge CLKA	0	0	0	86	86	86
DIA1	posedge CLKA	0	0	0	86	86	86
DIA2	posedge CLKA	0	0	0	86	86	86
DIA3	posedge CLKA	0	0	0	86	86	86
DIA4	posedge CLKA	0	0	0	86	86	86
DIA5	posedge CLKA	0	0	0	86	86	86
DIA6	posedge CLKA	0	0	0	86	86	86
DIA7	posedge CLKA	0	0	0	86	86	86
DIA8	posedge CLKA	0	0	0	86	86	86
DIB0	posedge CLKB	0	0	0	160	160	160
DIB1	posedge CLKB	0	0	0	160	160	160
DIB2	posedge CLKB	0	0	0	160	160	160
DIB3	posedge CLKB	0	0	0	160	160	160
DIB4	posedge CLKB	0	0	0	160	160	160
DIB5	posedge CLKB	0	0	0	160	160	160
DIB6	posedge CLKB	0	0	0	160	160	160
DIB7	posedge CLKB	0	0	0	160	160	160
DIB8	posedge CLKB	0	0	0	160	160	160
OCEA	posedge CLKA	0	0	0	131	131	131
OCEB	posedge CLKB	0	0	0	149	149	149
RSTA	posedge CLKA	351	351	351	0	0	0
RSTB	posedge CLKB	124	124	124	22	22	22
WEA	posedge CLKA	89	89	89	0	0	0
WEB	posedge CLKB	17	17	17	47	47	47

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	2739	2739	2739	183	183	183
negedge CLKB	2739	2739	2739	183	183	183
posedge CLKA	2739	2739	2739	183	183	183
posedge CLKB	2739	2739	2739	183	183	183

DP8KC:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4057	4057	4057	4057	4057	4057
CLKA	DOA1	4057	4057	4057	4057	4057	4057
CLKA	DOA2	4057	4057	4057	4057	4057	4057
CLKA	DOA3	4057	4057	4057	4057	4057	4057
CLKA	DOA4	4057	4057	4057	4057	4057	4057
CLKA	DOA5	4057	4057	4057	4057	4057	4057
CLKA	DOA6	4057	4057	4057	4057	4057	4057
CLKA	DOA7	4057	4057	4057	4057	4057	4057
CLKA	DOA8	4057	4057	4057	4057	4057	4057
CLKB	DOB0	827	827	827	827	827	827
CLKB	DOB1	827	827	827	827	827	827
CLKB	DOB2	827	827	827	827	827	827
CLKB	DOB3	827	827	827	827	827	827
CLKB	DOB4	827	827	827	827	827	827
CLKB	DOB5	827	827	827	827	827	827
CLKB	DOB6	827	827	827	827	827	827
CLKB	DOB7	827	827	827	827	827	827
CLKB	DOB8	827	827	827	827	827	827

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	75	75	75
ADA1	posedge CLKA	0	0	0	75	75	75
ADA10	posedge CLKA	0	0	0	75	75	75
ADA11	posedge CLKA	0	0	0	75	75	75
ADA12	posedge CLKA	0	0	0	75	75	75
ADA2	posedge CLKA	0	0	0	75	75	75
ADA3	posedge CLKA	0	0	0	75	75	75
ADA4	posedge CLKA	0	0	0	75	75	75
ADA5	posedge CLKA	0	0	0	75	75	75
ADA6	posedge CLKA	0	0	0	75	75	75
ADA7	posedge CLKA	0	0	0	75	75	75
ADA8	posedge CLKA	0	0	0	75	75	75
ADA9	posedge CLKA	0	0	0	75	75	75
ADB0	posedge CLKB	0	0	0	154	154	154
ADB1	posedge CLKB	0	0	0	154	154	154
ADB10	posedge CLKB	0	0	0	154	154	154
ADB11	posedge CLKB	0	0	0	154	154	154
ADB12	posedge CLKB	0	0	0	154	154	154
ADB2	posedge CLKB	0	0	0	154	154	154
ADB3	posedge CLKB	0	0	0	154	154	154
ADB4	posedge CLKB	0	0	0	154	154	154
ADB5	posedge CLKB	0	0	0	154	154	154
ADB6	posedge CLKB	0	0	0	154	154	154
ADB7	posedge CLKB	0	0	0	154	154	154
ADB8	posedge CLKB	0	0	0	154	154	154
ADB9	posedge CLKB	0	0	0	154	154	154
CEA	posedge CLKA	174	174	174	0	0	0
CEB	posedge CLKB	187	187	187	0	0	0
CSA0	posedge CLKA	116	116	116	0	0	0
CSA1	posedge CLKA	116	116	116	0	0	0
CSA2	posedge CLKA	116	116	116	0	0	0
CSB0	posedge CLKB	8	8	8	83	83	83
CSB1	posedge CLKB	8	8	8	83	83	83
CSB2	posedge CLKB	8	8	8	83	83	83
DIA0	posedge CLKA	0	0	0	86	86	86
DIA1	posedge CLKA	0	0	0	86	86	86
DIA2	posedge CLKA	0	0	0	86	86	86
DIA3	posedge CLKA	0	0	0	86	86	86
DIA4	posedge CLKA	0	0	0	86	86	86
DIA5	posedge CLKA	0	0	0	86	86	86
DIA6	posedge CLKA	0	0	0	86	86	86
DIA7	posedge CLKA	0	0	0	86	86	86
DIA8	posedge CLKA	0	0	0	86	86	86
DIB0	posedge CLKB	0	0	0	160	160	160
DIB1	posedge CLKB	0	0	0	160	160	160
DIB2	posedge CLKB	0	0	0	160	160	160
DIB3	posedge CLKB	0	0	0	160	160	160
DIB4	posedge CLKB	0	0	0	160	160	160
DIB5	posedge CLKB	0	0	0	160	160	160
DIB6	posedge CLKB	0	0	0	160	160	160
DIB7	posedge CLKB	0	0	0	160	160	160
DIB8	posedge CLKB	0	0	0	160	160	160
OCEA	posedge CLKA	0	0	0	131	131	131
OCEB	posedge CLKB	0	0	0	149	149	149
RSTA	posedge CLKA	351	351	351	0	0	0
RSTB	posedge CLKB	205	205	205	22	22	22
WEA	posedge CLKA	89	89	89	0	0	0
WEB	posedge CLKB	17	17	17	47	47	47

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	2739	2739	2739	183	183	183
negedge CLKB	2739	2739	2739	183	183	183
posedge CLKA	2739	2739	2739	183	183	183
posedge CLKB	2739	2739	2739	183	183	183

DP8KC:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	808	808	808	808	808	808
CLKA	DOA1	808	808	808	808	808	808
CLKA	DOA2	808	808	808	808	808	808
CLKA	DOA3	808	808	808	808	808	808
CLKA	DOA4	808	808	808	808	808	808
CLKA	DOA5	808	808	808	808	808	808
CLKA	DOA6	808	808	808	808	808	808
CLKA	DOA7	808	808	808	808	808	808
CLKA	DOA8	808	808	808	808	808	808
CLKB	DOB0	4254	4254	4254	4254	4254	4254
CLKB	DOB1	4254	4254	4254	4254	4254	4254
CLKB	DOB2	4254	4254	4254	4254	4254	4254
CLKB	DOB3	4254	4254	4254	4254	4254	4254
CLKB	DOB4	4254	4254	4254	4254	4254	4254
CLKB	DOB5	4254	4254	4254	4254	4254	4254
CLKB	DOB6	4254	4254	4254	4254	4254	4254
CLKB	DOB7	4254	4254	4254	4254	4254	4254
CLKB	DOB8	4254	4254	4254	4254	4254	4254

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	75	75	75
ADA1	posedge CLKA	0	0	0	75	75	75
ADA10	posedge CLKA	0	0	0	75	75	75
ADA11	posedge CLKA	0	0	0	75	75	75
ADA12	posedge CLKA	0	0	0	75	75	75
ADA2	posedge CLKA	0	0	0	75	75	75
ADA3	posedge CLKA	0	0	0	75	75	75
ADA4	posedge CLKA	0	0	0	75	75	75
ADA5	posedge CLKA	0	0	0	75	75	75
ADA6	posedge CLKA	0	0	0	75	75	75
ADA7	posedge CLKA	0	0	0	75	75	75
ADA8	posedge CLKA	0	0	0	75	75	75
ADA9	posedge CLKA	0	0	0	75	75	75
ADB0	posedge CLKB	0	0	0	154	154	154
ADB1	posedge CLKB	0	0	0	154	154	154
ADB10	posedge CLKB	0	0	0	154	154	154
ADB11	posedge CLKB	0	0	0	154	154	154
ADB12	posedge CLKB	0	0	0	154	154	154
ADB2	posedge CLKB	0	0	0	154	154	154
ADB3	posedge CLKB	0	0	0	154	154	154
ADB4	posedge CLKB	0	0	0	154	154	154
ADB5	posedge CLKB	0	0	0	154	154	154
ADB6	posedge CLKB	0	0	0	154	154	154
ADB7	posedge CLKB	0	0	0	154	154	154
ADB8	posedge CLKB	0	0	0	154	154	154
ADB9	posedge CLKB	0	0	0	154	154	154
CEA	posedge CLKA	174	174	174	0	0	0
CEB	posedge CLKB	187	187	187	0	0	0
CSA0	posedge CLKA	116	116	116	0	0	0
CSA1	posedge CLKA	116	116	116	0	0	0
CSA2	posedge CLKA	116	116	116	0	0	0
CSB0	posedge CLKB	8	8	8	83	83	83
CSB1	posedge CLKB	8	8	8	83	83	83
CSB2	posedge CLKB	8	8	8	83	83	83
DIA0	posedge CLKA	0	0	0	86	86	86
DIA1	posedge CLKA	0	0	0	86	86	86
DIA2	posedge CLKA	0	0	0	86	86	86
DIA3	posedge CLKA	0	0	0	86	86	86
DIA4	posedge CLKA	0	0	0	86	86	86
DIA5	posedge CLKA	0	0	0	86	86	86
DIA6	posedge CLKA	0	0	0	86	86	86
DIA7	posedge CLKA	0	0	0	86	86	86
DIA8	posedge CLKA	0	0	0	86	86	86
DIB0	posedge CLKB	0	0	0	160	160	160
DIB1	posedge CLKB	0	0	0	160	160	160
DIB2	posedge CLKB	0	0	0	160	160	160
DIB3	posedge CLKB	0	0	0	160	160	160
DIB4	posedge CLKB	0	0	0	160	160	160
DIB5	posedge CLKB	0	0	0	160	160	160
DIB6	posedge CLKB	0	0	0	160	160	160
DIB7	posedge CLKB	0	0	0	160	160	160
DIB8	posedge CLKB	0	0	0	160	160	160
OCEA	posedge CLKA	0	0	0	131	131	131
OCEB	posedge CLKB	0	0	0	149	149	149
RSTA	posedge CLKA	351	351	351	0	0	0
RSTB	posedge CLKB	124	124	124	22	22	22
WEA	posedge CLKA	89	89	89	0	0	0
WEB	posedge CLKB	17	17	17	47	47	47

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	2739	2739	2739	183	183	183
negedge CLKB	2739	2739	2739	183	183	183
posedge CLKA	2739	2739	2739	183	183	183
posedge CLKB	2739	2739	2739	183	183	183

DP8KC:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	808	808	808	808	808	808
CLKA	DOA1	808	808	808	808	808	808
CLKA	DOA2	808	808	808	808	808	808
CLKA	DOA3	808	808	808	808	808	808
CLKA	DOA4	808	808	808	808	808	808
CLKA	DOA5	808	808	808	808	808	808
CLKA	DOA6	808	808	808	808	808	808
CLKA	DOA7	808	808	808	808	808	808
CLKA	DOA8	808	808	808	808	808	808
CLKB	DOB0	827	827	827	827	827	827
CLKB	DOB1	827	827	827	827	827	827
CLKB	DOB2	827	827	827	827	827	827
CLKB	DOB3	827	827	827	827	827	827
CLKB	DOB4	827	827	827	827	827	827
CLKB	DOB5	827	827	827	827	827	827
CLKB	DOB6	827	827	827	827	827	827
CLKB	DOB7	827	827	827	827	827	827
CLKB	DOB8	827	827	827	827	827	827

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	75	75	75
ADA1	posedge CLKA	0	0	0	75	75	75
ADA10	posedge CLKA	0	0	0	75	75	75
ADA11	posedge CLKA	0	0	0	75	75	75
ADA12	posedge CLKA	0	0	0	75	75	75
ADA2	posedge CLKA	0	0	0	75	75	75
ADA3	posedge CLKA	0	0	0	75	75	75
ADA4	posedge CLKA	0	0	0	75	75	75
ADA5	posedge CLKA	0	0	0	75	75	75
ADA6	posedge CLKA	0	0	0	75	75	75
ADA7	posedge CLKA	0	0	0	75	75	75
ADA8	posedge CLKA	0	0	0	75	75	75
ADA9	posedge CLKA	0	0	0	75	75	75
ADB0	posedge CLKB	0	0	0	154	154	154
ADB1	posedge CLKB	0	0	0	154	154	154
ADB10	posedge CLKB	0	0	0	154	154	154
ADB11	posedge CLKB	0	0	0	154	154	154
ADB12	posedge CLKB	0	0	0	154	154	154
ADB2	posedge CLKB	0	0	0	154	154	154
ADB3	posedge CLKB	0	0	0	154	154	154
ADB4	posedge CLKB	0	0	0	154	154	154
ADB5	posedge CLKB	0	0	0	154	154	154
ADB6	posedge CLKB	0	0	0	154	154	154
ADB7	posedge CLKB	0	0	0	154	154	154
ADB8	posedge CLKB	0	0	0	154	154	154
ADB9	posedge CLKB	0	0	0	154	154	154
CEA	posedge CLKA	174	174	174	0	0	0
CEB	posedge CLKB	187	187	187	0	0	0
CSA0	posedge CLKA	116	116	116	0	0	0
CSA1	posedge CLKA	116	116	116	0	0	0
CSA2	posedge CLKA	116	116	116	0	0	0
CSB0	posedge CLKB	8	8	8	83	83	83
CSB1	posedge CLKB	8	8	8	83	83	83
CSB2	posedge CLKB	8	8	8	83	83	83
DIA0	posedge CLKA	0	0	0	86	86	86
DIA1	posedge CLKA	0	0	0	86	86	86
DIA2	posedge CLKA	0	0	0	86	86	86
DIA3	posedge CLKA	0	0	0	86	86	86
DIA4	posedge CLKA	0	0	0	86	86	86
DIA5	posedge CLKA	0	0	0	86	86	86
DIA6	posedge CLKA	0	0	0	86	86	86
DIA7	posedge CLKA	0	0	0	86	86	86
DIA8	posedge CLKA	0	0	0	86	86	86
DIB0	posedge CLKB	0	0	0	160	160	160
DIB1	posedge CLKB	0	0	0	160	160	160
DIB2	posedge CLKB	0	0	0	160	160	160
DIB3	posedge CLKB	0	0	0	160	160	160
DIB4	posedge CLKB	0	0	0	160	160	160
DIB5	posedge CLKB	0	0	0	160	160	160
DIB6	posedge CLKB	0	0	0	160	160	160
DIB7	posedge CLKB	0	0	0	160	160	160
DIB8	posedge CLKB	0	0	0	160	160	160
OCEA	posedge CLKA	0	0	0	131	131	131
OCEB	posedge CLKB	0	0	0	149	149	149
RSTA	posedge CLKA	351	351	351	0	0	0
RSTB	posedge CLKB	205	205	205	22	22	22
WEA	posedge CLKA	89	89	89	0	0	0
WEB	posedge CLKB	17	17	17	47	47	47

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	2739	2739	2739	183	183	183
negedge CLKB	2739	2739	2739	183	183	183
posedge CLKA	2739	2739	2739	183	183	183
posedge CLKB	2739	2739	2739	183	183	183

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4057	4057	4057	4057	4057	4057
CLKA	DOA1	4057	4057	4057	4057	4057	4057
CLKA	DOA2	4057	4057	4057	4057	4057	4057
CLKA	DOA3	4057	4057	4057	4057	4057	4057
CLKA	DOA4	4057	4057	4057	4057	4057	4057
CLKA	DOA5	4057	4057	4057	4057	4057	4057
CLKA	DOA6	4057	4057	4057	4057	4057	4057
CLKA	DOA7	4057	4057	4057	4057	4057	4057
CLKA	DOA8	4057	4057	4057	4057	4057	4057
CLKB	DOB0	4254	4254	4254	4254	4254	4254
CLKB	DOB1	4254	4254	4254	4254	4254	4254
CLKB	DOB2	4254	4254	4254	4254	4254	4254
CLKB	DOB3	4254	4254	4254	4254	4254	4254
CLKB	DOB4	4254	4254	4254	4254	4254	4254
CLKB	DOB5	4254	4254	4254	4254	4254	4254
CLKB	DOB6	4254	4254	4254	4254	4254	4254
CLKB	DOB7	4254	4254	4254	4254	4254	4254
CLKB	DOB8	4254	4254	4254	4254	4254	4254

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	75	75	75
ADA1	posedge CLKA	0	0	0	75	75	75
ADA10	posedge CLKA	0	0	0	75	75	75
ADA11	posedge CLKA	0	0	0	75	75	75
ADA12	posedge CLKA	0	0	0	75	75	75
ADA2	posedge CLKA	0	0	0	75	75	75
ADA3	posedge CLKA	0	0	0	75	75	75
ADA4	posedge CLKA	0	0	0	75	75	75
ADA5	posedge CLKA	0	0	0	75	75	75
ADA6	posedge CLKA	0	0	0	75	75	75
ADA7	posedge CLKA	0	0	0	75	75	75
ADA8	posedge CLKA	0	0	0	75	75	75
ADA9	posedge CLKA	0	0	0	75	75	75
ADB0	posedge CLKB	0	0	0	154	154	154
ADB1	posedge CLKB	0	0	0	154	154	154
ADB10	posedge CLKB	0	0	0	154	154	154
ADB11	posedge CLKB	0	0	0	154	154	154
ADB12	posedge CLKB	0	0	0	154	154	154
ADB2	posedge CLKB	0	0	0	154	154	154
ADB3	posedge CLKB	0	0	0	154	154	154
ADB4	posedge CLKB	0	0	0	154	154	154
ADB5	posedge CLKB	0	0	0	154	154	154
ADB6	posedge CLKB	0	0	0	154	154	154
ADB7	posedge CLKB	0	0	0	154	154	154
ADB8	posedge CLKB	0	0	0	154	154	154
ADB9	posedge CLKB	0	0	0	154	154	154
CEA	posedge CLKA	174	174	174	0	0	0
CEB	posedge CLKB	187	187	187	0	0	0
CSA0	posedge CLKA	116	116	116	0	0	0
CSA1	posedge CLKA	116	116	116	0	0	0
CSA2	posedge CLKA	116	116	116	0	0	0
CSB0	posedge CLKB	8	8	8	83	83	83
CSB1	posedge CLKB	8	8	8	83	83	83
CSB2	posedge CLKB	8	8	8	83	83	83
DIA0	posedge CLKA	0	0	0	86	86	86
DIA1	posedge CLKA	0	0	0	86	86	86
DIA2	posedge CLKA	0	0	0	86	86	86
DIA3	posedge CLKA	0	0	0	86	86	86
DIA4	posedge CLKA	0	0	0	86	86	86
DIA5	posedge CLKA	0	0	0	86	86	86
DIA6	posedge CLKA	0	0	0	86	86	86
DIA7	posedge CLKA	0	0	0	86	86	86
DIA8	posedge CLKA	0	0	0	86	86	86
DIB0	posedge CLKB	0	0	0	160	160	160
DIB1	posedge CLKB	0	0	0	160	160	160
DIB2	posedge CLKB	0	0	0	160	160	160
DIB3	posedge CLKB	0	0	0	160	160	160
DIB4	posedge CLKB	0	0	0	160	160	160
DIB5	posedge CLKB	0	0	0	160	160	160
DIB6	posedge CLKB	0	0	0	160	160	160
DIB7	posedge CLKB	0	0	0	160	160	160
DIB8	posedge CLKB	0	0	0	160	160	160
OCEA	posedge CLKA	0	0	0	131	131	131
OCEB	posedge CLKB	0	0	0	149	149	149
RSTA	posedge CLKA	351	351	351	0	0	0
RSTB	posedge CLKB	124	124	124	22	22	22
WEA	posedge CLKA	89	89	89	0	0	0
WEB	posedge CLKB	17	17	17	47	47	47

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	2739	2739	2739	183	183	183
negedge CLKB	2739	2739	2739	183	183	183
posedge CLKA	2739	2739	2739	183	183	183
posedge CLKB	2739	2739	2739	183	183	183

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4057	4057	4057	4057	4057	4057
CLKA	DOA1	4057	4057	4057	4057	4057	4057
CLKA	DOA2	4057	4057	4057	4057	4057	4057
CLKA	DOA3	4057	4057	4057	4057	4057	4057
CLKA	DOA4	4057	4057	4057	4057	4057	4057
CLKA	DOA5	4057	4057	4057	4057	4057	4057
CLKA	DOA6	4057	4057	4057	4057	4057	4057
CLKA	DOA7	4057	4057	4057	4057	4057	4057
CLKA	DOA8	4057	4057	4057	4057	4057	4057
CLKB	DOB0	4254	4254	4254	4254	4254	4254
CLKB	DOB1	4254	4254	4254	4254	4254	4254
CLKB	DOB2	4254	4254	4254	4254	4254	4254
CLKB	DOB3	4254	4254	4254	4254	4254	4254
CLKB	DOB4	4254	4254	4254	4254	4254	4254
CLKB	DOB5	4254	4254	4254	4254	4254	4254
CLKB	DOB6	4254	4254	4254	4254	4254	4254
CLKB	DOB7	4254	4254	4254	4254	4254	4254
CLKB	DOB8	4254	4254	4254	4254	4254	4254

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	75	75	75
ADA1	posedge CLKA	0	0	0	75	75	75
ADA10	posedge CLKA	0	0	0	75	75	75
ADA11	posedge CLKA	0	0	0	75	75	75
ADA12	posedge CLKA	0	0	0	75	75	75
ADA2	posedge CLKA	0	0	0	75	75	75
ADA3	posedge CLKA	0	0	0	75	75	75
ADA4	posedge CLKA	0	0	0	75	75	75
ADA5	posedge CLKA	0	0	0	75	75	75
ADA6	posedge CLKA	0	0	0	75	75	75
ADA7	posedge CLKA	0	0	0	75	75	75
ADA8	posedge CLKA	0	0	0	75	75	75
ADA9	posedge CLKA	0	0	0	75	75	75
ADB0	posedge CLKB	0	0	0	154	154	154
ADB1	posedge CLKB	0	0	0	154	154	154
ADB10	posedge CLKB	0	0	0	154	154	154
ADB11	posedge CLKB	0	0	0	154	154	154
ADB12	posedge CLKB	0	0	0	154	154	154
ADB2	posedge CLKB	0	0	0	154	154	154
ADB3	posedge CLKB	0	0	0	154	154	154
ADB4	posedge CLKB	0	0	0	154	154	154
ADB5	posedge CLKB	0	0	0	154	154	154
ADB6	posedge CLKB	0	0	0	154	154	154
ADB7	posedge CLKB	0	0	0	154	154	154
ADB8	posedge CLKB	0	0	0	154	154	154
ADB9	posedge CLKB	0	0	0	154	154	154
CEA	posedge CLKA	174	174	174	0	0	0
CEB	posedge CLKB	187	187	187	0	0	0
CSA0	posedge CLKA	116	116	116	0	0	0
CSA1	posedge CLKA	116	116	116	0	0	0
CSA2	posedge CLKA	116	116	116	0	0	0
CSB0	posedge CLKB	8	8	8	83	83	83
CSB1	posedge CLKB	8	8	8	83	83	83
CSB2	posedge CLKB	8	8	8	83	83	83
DIA0	posedge CLKA	0	0	0	86	86	86
DIA1	posedge CLKA	0	0	0	86	86	86
DIA2	posedge CLKA	0	0	0	86	86	86
DIA3	posedge CLKA	0	0	0	86	86	86
DIA4	posedge CLKA	0	0	0	86	86	86
DIA5	posedge CLKA	0	0	0	86	86	86
DIA6	posedge CLKA	0	0	0	86	86	86
DIA7	posedge CLKA	0	0	0	86	86	86
DIA8	posedge CLKA	0	0	0	86	86	86
DIB0	posedge CLKB	0	0	0	160	160	160
DIB1	posedge CLKB	0	0	0	160	160	160
DIB2	posedge CLKB	0	0	0	160	160	160
DIB3	posedge CLKB	0	0	0	160	160	160
DIB4	posedge CLKB	0	0	0	160	160	160
DIB5	posedge CLKB	0	0	0	160	160	160
DIB6	posedge CLKB	0	0	0	160	160	160
DIB7	posedge CLKB	0	0	0	160	160	160
DIB8	posedge CLKB	0	0	0	160	160	160
OCEA	posedge CLKA	0	0	0	131	131	131
OCEB	posedge CLKB	0	0	0	149	149	149
RSTA	posedge CLKA	351	351	351	0	0	0
RSTB	posedge CLKB	124	124	124	22	22	22
WEA	posedge CLKA	89	89	89	0	0	0
WEB	posedge CLKB	17	17	17	47	47	47

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	2739	2739	2739	183	183	183
negedge CLKB	4166	4166	4166	120	120	120
posedge CLKA	2739	2739	2739	183	183	183
posedge CLKB	4166	4166	4166	120	120	120

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4057	4057	4057	4057	4057	4057
CLKA	DOA1	4057	4057	4057	4057	4057	4057
CLKA	DOA2	4057	4057	4057	4057	4057	4057
CLKA	DOA3	4057	4057	4057	4057	4057	4057
CLKA	DOA4	4057	4057	4057	4057	4057	4057
CLKA	DOA5	4057	4057	4057	4057	4057	4057
CLKA	DOA6	4057	4057	4057	4057	4057	4057
CLKA	DOA7	4057	4057	4057	4057	4057	4057
CLKA	DOA8	4057	4057	4057	4057	4057	4057
CLKB	DOB0	4254	4254	4254	4254	4254	4254
CLKB	DOB1	4254	4254	4254	4254	4254	4254
CLKB	DOB2	4254	4254	4254	4254	4254	4254
CLKB	DOB3	4254	4254	4254	4254	4254	4254
CLKB	DOB4	4254	4254	4254	4254	4254	4254
CLKB	DOB5	4254	4254	4254	4254	4254	4254
CLKB	DOB6	4254	4254	4254	4254	4254	4254
CLKB	DOB7	4254	4254	4254	4254	4254	4254
CLKB	DOB8	4254	4254	4254	4254	4254	4254

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	75	75	75
ADA1	posedge CLKA	0	0	0	75	75	75
ADA10	posedge CLKA	0	0	0	75	75	75
ADA11	posedge CLKA	0	0	0	75	75	75
ADA12	posedge CLKA	0	0	0	75	75	75
ADA2	posedge CLKA	0	0	0	75	75	75
ADA3	posedge CLKA	0	0	0	75	75	75
ADA4	posedge CLKA	0	0	0	75	75	75
ADA5	posedge CLKA	0	0	0	75	75	75
ADA6	posedge CLKA	0	0	0	75	75	75
ADA7	posedge CLKA	0	0	0	75	75	75
ADA8	posedge CLKA	0	0	0	75	75	75
ADA9	posedge CLKA	0	0	0	75	75	75
ADB0	posedge CLKB	0	0	0	154	154	154
ADB1	posedge CLKB	0	0	0	154	154	154
ADB10	posedge CLKB	0	0	0	154	154	154
ADB11	posedge CLKB	0	0	0	154	154	154
ADB12	posedge CLKB	0	0	0	154	154	154
ADB2	posedge CLKB	0	0	0	154	154	154
ADB3	posedge CLKB	0	0	0	154	154	154
ADB4	posedge CLKB	0	0	0	154	154	154
ADB5	posedge CLKB	0	0	0	154	154	154
ADB6	posedge CLKB	0	0	0	154	154	154
ADB7	posedge CLKB	0	0	0	154	154	154
ADB8	posedge CLKB	0	0	0	154	154	154
ADB9	posedge CLKB	0	0	0	154	154	154
CEA	posedge CLKA	174	174	174	0	0	0
CEB	posedge CLKB	187	187	187	0	0	0
CSA0	posedge CLKA	116	116	116	0	0	0
CSA1	posedge CLKA	116	116	116	0	0	0
CSA2	posedge CLKA	116	116	116	0	0	0
CSB0	posedge CLKB	8	8	8	83	83	83
CSB1	posedge CLKB	8	8	8	83	83	83
CSB2	posedge CLKB	8	8	8	83	83	83
DIA0	posedge CLKA	0	0	0	86	86	86
DIA1	posedge CLKA	0	0	0	86	86	86
DIA2	posedge CLKA	0	0	0	86	86	86
DIA3	posedge CLKA	0	0	0	86	86	86
DIA4	posedge CLKA	0	0	0	86	86	86
DIA5	posedge CLKA	0	0	0	86	86	86
DIA6	posedge CLKA	0	0	0	86	86	86
DIA7	posedge CLKA	0	0	0	86	86	86
DIA8	posedge CLKA	0	0	0	86	86	86
DIB0	posedge CLKB	0	0	0	160	160	160
DIB1	posedge CLKB	0	0	0	160	160	160
DIB2	posedge CLKB	0	0	0	160	160	160
DIB3	posedge CLKB	0	0	0	160	160	160
DIB4	posedge CLKB	0	0	0	160	160	160
DIB5	posedge CLKB	0	0	0	160	160	160
DIB6	posedge CLKB	0	0	0	160	160	160
DIB7	posedge CLKB	0	0	0	160	160	160
DIB8	posedge CLKB	0	0	0	160	160	160
OCEA	posedge CLKA	0	0	0	131	131	131
OCEB	posedge CLKB	0	0	0	149	149	149
RSTA	posedge CLKA	351	351	351	0	0	0
RSTB	posedge CLKB	124	124	124	22	22	22
WEA	posedge CLKA	89	89	89	0	0	0
WEB	posedge CLKB	17	17	17	47	47	47

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	2739	2739	2739	183	183	183
negedge CLKB	2739	2739	2739	183	183	183
posedge CLKA	2739	2739	2739	183	183	183
posedge CLKB	2739	2739	2739	183	183	183

PIO:IOTYPE=LVCMOS12

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1037	1176	1315	1037	1176	1315
PADDO	PAD	7624	7699	7774	7624	7699	7774
PADDT	PAD	4397	8598	12800	4397	8598	12800

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	5500	5500	5500	91	91	91
posedge PAD	5500	5500	5500	91	91	91

PIO:IOTYPE=LVCMOS15

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	2298	2340	2383	2298	2340	2383
PADDO	PAD	4875	5041	5207	4875	5041	5207
PADDT	PAD	3221	5476	7732	3221	5476	7732

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVCMOS18

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1740	1753	1767	1740	1753	1767
PADDO	PAD	3735	3891	4048	3735	3891	4048
PADDT	PAD	2742	4200	5658	2742	4200	5658

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVCMOS25

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1223	1297	1372	1223	1297	1372
PADDO	PAD	3220	3334	3448	3220	3334	3448
PADDT	PAD	2349	3502	4656	2349	3502	4656

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVCMOS33

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1007	1069	1132	1007	1069	1132
PADDO	PAD	2611	2704	2797	2611	2704	2797
PADDT	PAD	2387	3283	4180	2387	3283	4180

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVDS

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1087	1105	1123	1087	1105	1123
PADDO	PAD	2803	2803	2804	2803	2803	2804
PADDT	PAD	2906	4040	5174	2906	4040	5174

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL15_I

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1087	1105	1123	1087	1105	1123
PADDO	PAD	2803	2803	2804	2803	2803	2804
PADDT	PAD	2906	4040	5174	2906	4040	5174

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL15_II

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1087	1105	1123	1087	1105	1123
PADDO	PAD	2803	2803	2804	2803	2803	2804
PADDT	PAD	2906	4040	5174	2906	4040	5174

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL18_I

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1282	1330	1378	1282	1330	1378
PADDO	PAD	3136	3311	3486	3136	3311	3486
PADDT	PAD	3754	4790	5827	3754	4790	5827

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL18_II

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1087	1105	1123	1087	1105	1123
PADDO	PAD	2803	2803	2804	2803	2803	2804
PADDT	PAD	2906	4040	5174	2906	4040	5174

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

SLICE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A0	F0	281	344	408	281	344	408
A0	F1	552	618	684	552	618	684
A0	FCO	636	711	787	636	711	787
A0	OFX0	437	519	601	437	519	601
A1	F1	281	344	408	281	344	408
A1	FCO	552	618	684	552	618	684
A1	OFX0	437	519	601	437	519	601
B0	F0	281	344	408	281	344	408
B0	F1	552	618	684	552	618	684
B0	FCO	636	711	787	636	711	787
B0	OFX0	437	519	601	437	519	601
B1	F1	281	344	408	281	344	408
B1	FCO	552	618	684	552	618	684
B1	OFX0	437	519	601	437	519	601
C0	F0	281	344	408	281	344	408
C0	F1	552	618	684	552	618	684
C0	FCO	636	711	787	636	711	787
C0	OFX0	437	519	601	437	519	601
C1	F1	281	344	408	281	344	408
C1	FCO	552	618	684	552	618	684
C1	OFX0	437	519	601	437	519	601
CLK	Q0	320	343	367	320	343	367
CLK	Q1	320	343	367	320	343	367
D0	F0	281	344	408	281	344	408
D0	F1	552	618	684	552	618	684
D0	FCO	636	711	787	636	711	787
D0	OFX0	437	519	601	437	519	601
D1	F1	281	344	408	281	344	408
D1	FCO	552	618	684	552	618	684
D1	OFX0	437	519	601	437	519	601
FCI	F0	364	407	450	364	407	450
FCI	F1	399	447	495	399	447	495
FCI	FCO	94	112	130	94	112	130
FXA	OFX1	163	184	205	163	184	205
FXB	OFX1	163	184	205	163	184	205
LSR	Q0	625	698	772	625	698	772
M0	OFX0	248	280	313	248	280	313
M1	OFX1	248	280	313	248	280	313
WCK	F0	854	962	1070	854	962	1070
WCK	F1	854	962	1070	854	962	1070

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	negedge CLK	190	213	236	0	0	0
CE	posedge CLK	176	196	217	0	0	0
DI0	negedge CLK	104	118	133	0	0	0
DI0	posedge CLK	104	118	133	0	0	0
DI1	posedge CLK	104	118	133	0	0	0
LSR	negedge CLK	191	209	228	0	0	0
LSR	posedge CLK	186	204	223	0	0	0
LSR	posedge CLK	564	564	564	0	0	0
M0	posedge CLK	202	230	258	0	0	0
M1	negedge CLK	202	230	258	0	0	0
M1	posedge CLK	202	230	258	0	0	0
WAD0	posedge WCK	0	0	0	364	384	404
WAD1	posedge WCK	0	0	0	364	384	404
WAD2	posedge WCK	0	0	0	364	384	404
WAD3	posedge WCK	0	0	0	364	384	404
WD0	posedge WCK	0	0	0	366	387	408
WD1	posedge WCK	0	0	0	366	387	408
WRE	posedge WCK	162	180	198	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1000	1000	1000	500	500	500
negedge LSR	3000	3000	3000	167	167	167
negedge WCK	1000	1000	1000	500	500	500
posedge CLK	1000	1000	1000	500	500	500
posedge LSR	3000	3000	3000	167	167	167
posedge WCK	1000	1000	1000	500	500	500

MachXO2 Speed Grade -6 Cell Timings

Contents

DP8KC:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

Setup/Hold Checks

Width Checks

PIO:IOTYPE=LVCMOS12

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS15

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS18

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS25

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS33

Propagation Delays

Width Checks

PIO:IOTYPE=LVDS

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL15_I

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL15_II

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL18_I

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL18_II

Propagation Delays

Width Checks

SLICE

Propagation Delays

Setup/Hold Checks

Width Checks