PIC_B_DUMMY_VIQ_VREF Bit Data

 
 
 
 
 
 
 
 
 
 
 
 
 
 
V
V
 
 
V
V
V
V
 
 
V
I
A
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
V
V
 
 
 
 
V
V
 
 
 
 
 
 
 
 
 
 
I
R
 
 
 
 
V
V
V
V
V
V
 
 
V
V
V
I
 
 
A
 
 
 
 
V
 
 
 
 
V
V
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
P
 
 
P
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
D
M
D
D
 
 
E
E
E
G
 
 
E
E
E
G
 
 
D
M
D
D
 
 
 
 
 
 
 
 

Mux driving JINCK0

Source F3B16
G_JPCLKT20 -
JPADDI0 -
N1_JINECK0 -
DLLDEL0 1

Mux driving JINCK1

Source F1B4
G_JPCLKT21 -
JPADDI1 -
N1_JINECK1 -
DLLDEL1 1

Mux driving N1_ECLKI0

Source F0B44 F1B44 F2B44
N1_JPLLCLKOP1 1 - -
N1_JECLKCIB0 - 1 -
N1_JPLLCLKOS1 1 1 -
N1_JECLKBRG0 - - 1
N1_JPLLCLKOS0 1 - 1
N1_JPLLCLKOP0 - 1 1
N1_JINECK0 1 1 1

Mux driving N1_ECLKI1

Source F0B45 F1B45 F2B45
N1_JPLLCLKOP1 1 - -
N1_JECLKCIB1 - 1 -
N1_JPLLCLKOS1 1 1 -
N1_JECLKBRG1 - - 1
N1_JPLLCLKOS0 1 - 1
N1_JPLLCLKOP0 - 1 1
N1_JINECK1 1 1 1

Mux driving N1_JPLLCLKFB0

Source F3B23
4300D_N21E15_JCLKFB4 -
4300D_N21W14_JCLKFB4 -
9400D_N30E23_JCLKFB4 -
9400D_N30W23_JCLKFB4 -
G_BECLK0 -
N1_CLKFBBUF0 1

Mux driving N1_JPLLCLKFB1

Source F0B24
4300D_N21E15_JCLKFB2 -
4300D_N21W14_JCLKFB2 -
9400D_N30E23_JCLKFB2 -
9400D_N30W23_JCLKFB2 -
G_BECLK1 -
N1_CLKFBBUF1 1

Configuration word BDLLDEL0.DEL_VAL

Default value: 7'b0000000

BDLLDEL0.DEL_VAL[0]F0B15
BDLLDEL0.DEL_VAL[1]F1B15
BDLLDEL0.DEL_VAL[2]F2B15
BDLLDEL0.DEL_VAL[3]F3B15
BDLLDEL0.DEL_VAL[4]F0B16
BDLLDEL0.DEL_VAL[5]F1B16
BDLLDEL0.DEL_VAL[6]F2B16

Configuration word BDLLDEL1.DEL_VAL

Default value: 7'b0000000

BDLLDEL1.DEL_VAL[0]F2B2
BDLLDEL1.DEL_VAL[1]F3B2
BDLLDEL1.DEL_VAL[2]F0B3
BDLLDEL1.DEL_VAL[3]F1B3
BDLLDEL1.DEL_VAL[4]F2B3
BDLLDEL1.DEL_VAL[5]F3B3
BDLLDEL1.DEL_VAL[6]F0B4

Configuration Setting BANK.DIFF_REF

Default value: OFF

Value F5B13
OFF 0
ON 1

Configuration Setting BANK.INRD

Default value: OFF

Value F4B13
OFF 0
ON 1

Configuration Setting BANK.VCCIO

Default value: NONE

Value F4B10 F4B11 F4B18 F5B10 F5B11 F5B14 F5B17 F5B18
NONE 0 0 0 0 0 0 0 0
1.2 1 1 1 1 1 1 1 1
1.5 0 1 1 1 0 1 1 1
1.8 0 0 1 1 0 1 1 1
2.5 0 0 1 0 0 1 1 1
3.3 0 0 1 0 0 0 1 1

Configuration Setting BANK.VREF

Default value: OFF

Value F4B14
OFF 0
ON 1

Configuration Setting BCLKDIV0.DIV

Value F0B43 F2B43 F3B43
2.0 0 0 1
3.5 0 1 0
4.0 1 0 0

Configuration Setting BCLKDIV0.GSR

Default value: ENABLED

Value F3B44
DISABLED 1
ENABLED 0

Configuration Setting BCLKDIV1.DIV

Value F0B46 F2B46 F3B46
2.0 0 1 0
3.5 0 0 1
4.0 1 0 0

Configuration Setting BCLKDIV1.GSR

Default value: ENABLED

Value F3B45
DISABLED 1
ENABLED 0

Configuration Setting BDLLDEL0.DEL_ADJ

Default value: PLUS

Value F0B17
MINUS 1
PLUS 0

Configuration Setting BDLLDEL1.DEL_ADJ

Default value: PLUS

Value F2B4
MINUS 1
PLUS 0

Configuration Setting BECLKSYNC0.MODE

Default value: NONE

Value F1B43
NONE -
ECLKSYNCA 1

Configuration Setting BECLKSYNC1.MODE

Default value: NONE

Value F1B46
NONE -
ECLKSYNCA 1

Fixed Connections

SourceSink
N1_Z0_CLKFBBUF→ N1_CLKFBBUF0
N1_Z1_CLKFBBUF→ N1_CLKFBBUF1
N1_JECLKO0_ECLKSYNC→ N1_CLKI0_CLKDIV
N1_JECLKO1_ECLKSYNC→ N1_CLKI1_CLKDIV
CLKO0_DLLDEL→ DLLDEL0
CLKO1_DLLDEL→ DLLDEL1
N1_ECLKI0→ N1_ECLKI0_ECLKSYNC
N1_ECLKI1→ N1_ECLKI1_ECLKSYNC
N1_JECLKO0_ECLKSYNC→ G_BECLK0
N1_JECLKO1_ECLKSYNC→ G_BECLK1
N1_JCDIV10_CLKDIV→ G_JBCDIV10
N1_JCDIV11_CLKDIV→ G_JBCDIV11
N1_JCDIVX0_CLKDIV→ G_JBCDIVX0
N1_JCDIVX1_CLKDIV→ G_JBCDIVX1
4300D_N21W14_JCLKOP_PLL→ N1_JA0_CLKFBBUF
9400D_N30W23_JCLKOP_PLL→ N1_JA0_CLKFBBUF
4300D_N21E15_JCLKOP_PLL→ N1_JA1_CLKFBBUF
9400D_N30E23_JCLKOP_PLL→ N1_JA1_CLKFBBUF
N1_JA0→ N1_JALIGNWD0_CLKDIV
N1_JA1→ N1_JALIGNWD1_CLKDIV
4300D_N1W14_JDQSDEL_DQSDLL→ JDQSDEL0_DLLDEL
9400D_N1W23_JDQSDEL_DQSDLL→ JDQSDEL0_DLLDEL
4300D_N1W14_JDQSDEL_DQSDLL→ JDQSDEL1_DLLDEL
9400D_N1W23_JDQSDEL_DQSDLL→ JDQSDEL1_DLLDEL
N1_JCLK2→ N1_JECLKCIB0
N1_JCLK3→ N1_JECLKCIB1
N1_ECLKI0_ECLKSYNC→ N1_JECLKO0_ECLKSYNC
N1_ECLKI1_ECLKSYNC→ N1_JECLKO1_ECLKSYNC
N1_JCDIVX0_CLKDIV→ N1_JF0
N1_JCDIV10_CLKDIV→ N1_JF1
N1_JCDIVX1_CLKDIV→ N1_JF2
N1_JCDIV11_CLKDIV→ N1_JF3
JINCK0→ N1_JINECK0
JINCK1→ N1_JINECK1
4300D_N21W14_JCLKOP_PLL→ N1_JPLLCLKOP0
9400D_N30W23_JCLKOP_PLL→ N1_JPLLCLKOP0
4300D_N21E15_JCLKOP_PLL→ N1_JPLLCLKOP1
9400D_N30E23_JCLKOP_PLL→ N1_JPLLCLKOP1
4300D_N21W14_JCLKOS_PLL→ N1_JPLLCLKOS0
9400D_N30W23_JCLKOS_PLL→ N1_JPLLCLKOS0
4300D_N21E15_JCLKOS_PLL→ N1_JPLLCLKOS1
9400D_N30E23_JCLKOS_PLL→ N1_JPLLCLKOS1
N1_JECLKO0_ECLKSYNC→ N1_JQ4
N1_JECLKO1_ECLKSYNC→ N1_JQ5
N1_JA2→ N1_JRST0_CLKDIV
N1_JA3→ N1_JRST1_CLKDIV
N1_JC5→ N1_JSTOP0_ECLKSYNC
N1_JD5→ N1_JSTOP1_ECLKSYNC